Magnetic memories MRAM have been the object of a renewed interest with the discovery of magnetic tunnel junctions (MTJ) having a strong magnetoresistance at ambient temperature. These magnetic random access memories present many advantages such as speed (a few nanoseconds of duration of writing and reading), non volatility, and insensitivity to ionizing radiations. Consequently, they are increasingly replacing memory that uses more conventional technology based on the charge state of a capacitor (DRAM, SRAM, FLASH).
In conventional MTJ based MRAM, the memory cell consists of an element having a junction consisting of a stack of several alternatively magnetic and non-magnetic metallic layers. Examples of conventional MTJ based MRAM devices are described in U.S. Pat. No. 5,640,343. In their simplest forms, junctions of MTJ based MRAM are made of two magnetic layers of different coercivity separated by an insulating thin layer where the first layer, the reference layer, is characterized by a fixed magnetization and the second layer, the storage layer, is characterized by a magnetization which direction can be changed. When the respective magnetizations of the reference layers and the storage layer are antiparallel, the resistance of the junction is high. On the other hand, when the respective magnetizations are parallel, the resistance becomes low.
Preferentially, the reference layer and the storage layer are made of 3d metals such as Fe, Co or Ni or their alloys. Eventually, boron can be added in the layer composition in order obtain an amorphous morphology and a flat interface. The insulating layer typically consists of alumina (Al2O3) or magnesium oxide (MgO). Preferentially, the reference layer can itself consist of several layers as described, for instance, in U.S. Pat. No. 5,583,725 in order to form a synthetic antiferromagnetic layer. A double tunnel junction as described in the paper by Y. Saito et al., Journal of Magnetism and Magnetic Materials Vol. 223 (2001), p. 293, can also be used. In this case, the storage layer is sandwiched between two thin insulating layers with two reference layers located on each opposite sides of the thin insulating layers.
FIG. 1 shows a memory cell 1 of a conventional MTJ based MRAM where a junction 2, comprising a storage layer 21, an insulating layer 22 and a reference layer 23, is placed between a selection CMOS transistor 3 and a word current line 4. A bit current line 5 is placed orthogonal with the word current line 4. When electrical currents flow in the word and bit current lines 4, 5, the word and bit magnetic fields 41 and 51 are respectively produced. Electrical currents are typically short current pulses from 2 to 5 nanoseconds having a magnitude on the order of 10 mA. An additional control current line 6 is intended to control the opening or the closing of the transistor 3 in order to address each memory cell individually.
During the writing process, the transistor 3 is in the blocked mode (OFF) and no current flows through the junction 2. The intensity of the current pulses and their synchronization are adjusted so that only the magnetization of the storage layer 21 located at the crossing of the two current lines can switch, under the combined effect of the word and bit magnetic fields 41 and 51.
During the reading process, the transistor 3 is in the saturated mode (ON) and a junction current will flows through the junction 2 allowing the measurement of the junction resistance of the memory cell 1. The state of the memory cell 1 is determined by comparing the measured resistance with the resistance of a reference memory cell. For example, a low junction resistance will be measured when the magnetization of the storage layer 21 is parallel to the magnetization of the reference layer 23 corresponding to a value of “0”. Conversely, a magnetization of the storage layer 21, antiparallel to the magnetization of the reference layer 23, will yield a high junction resistance corresponding to a value of “1”.
The basic structure of this type of conventional MTJ based MRAM is described in details in U.S. Pat. No. 4,949,039 and U.S. Pat. No. 5,159,513 while U.S. Pat. No. 5,343,422 is concerned with the implementation of a random-access memory (RAM) based on a MTJ based MRAM structure.
The type of writing mechanism described above has several disadvantages. In particular since the reversal of the magnetization of the storage layer 21 is produced under the effect of external fields and since the reversal fields are statistically distributed, it is possible to accidentally reverse certain neighboring junctions simply by the effect of the magnetic field produced along a lower or upper word or bit current line 4, 5. For high density memories with memory cells having submicronic dimensions, the number of addressing errors may be high. The reduction in the memory cells size will lead to an increase in the value of the individual reversal field and require a higher current to write memory cells, increasing the circuit consumption. Consequently, the writing mode using two current lines limits the integration density.
An improvement with respect to the above MTJ based MRAM structure is the thermally assisted writing process described in US2005002228 and represented in FIG. 2. The particularity of the junction 2 of such thermally assisted MRAM is that both the reference layer 23 and the storage layer 21 are exchange biased. More precisely, the reference and storage layers 23, 21 are pinned by interaction with an adjacent antiferromagnetic reference layer 24 and antiferromagnetic storage layer 21b respectively, where the blocking temperature TBS of the antiferromagnetic storage layer 21b is smaller than the blocking temperature TBR of the antiferromagnetic reference layer 24.
During the thermally-assisted writing process, a junction current pulse 31 having a magnitude comprised between 105 A/cm2 and 107 A/cm2 and lasting several nanoseconds is sent through a connecting current line 7 and the junction 2 (with transistor ON), rising the temperature of the junction to about 120 to 200° C., lying between TBS and TBR where the magnetic coupling between the ferromagnetic storage layer 21 and antiferromagnetic storage layer 21b disappears. The junction 2 is then cooled while a moderate word magnetic field 41 is applied by flowing a current in the word current line 4, allowing for the reversal of the magnetization of the storage layer 21.
The reading process is performed by making a measurement current flow through the junction (with the transistor ON) in order to measure the junction resistance and deduces the orientation of the magnetization of the storage layer from said resistance value. The measurement current is lower than the one used during the writing process resulting in less heating of the junction.
A similar MTJ based MRAM structure with the thermally assisted writing process is disclosed in US2005180202. Here a magnetic element comprises a ferromagnetic free layer, a ferromagnetic pinned layer, and a spacer layer 120 between the free layer and the pinned layer. The magnetic element further comprises a heat assisted switching layer exchange coupling the free layer 130 and pins the magnetization of the free layer 130 at temperatures below a blocking temperature of about 150° C.
In contrast with the conventional MTJ based MRAM, the thermally assisted MTJ based MRAM structure described above is characterized by a considerably improved thermal stability of the storage layer 21 due to the pinning of the antiferromagnetic storage layer 21b. An improved writing selectivity is also achieved due to the selective heating of the memory cell to be written in comparison with the neighboring memory cells remaining at ambient temperature. The thermally assisted MTJ based MRAM structure also allows for a better stability in a zero magnetic field (retention) by using materials with high magnetic anisotropy at ambient temperature; a higher integration density without affecting its stability limit; and reduced power consumption during the writing process since the power required to heat the memory cell 1 is less than the one needed to generate magnetization in the conventional MTJ based MRAM structure.
However, with the thermally assisted MTJ based MRAM described above, the current to be supplied in order to generate a magnetic field that is suitable for switching the storage layer magnetization, i.e., in the order of 30-50 Oe, is in the mA range. This current is still too large for low power consumption applications and will also increase continuously as the cell size is reduced.
Alternative thermally assisted MTJ based MRAM structures avoiding the use of current word and bit lines by using a spin polarized current for the switching of the magnetization of the storage layer have been proposed in US-A-20050104101, U.S. Pat. No. 6,603,677 B2 and U.S. Pat. No. 6,532,164 B2. The solutions proposed however are still not suitable for low-power applications and cannot guarantee the stability of the information for long time while preserving a reasonable low aspect ratio of the memory cell.